Ga2O3(Gd2O3) as Charge-Trapping Layer for Nonvolatile Memory Applications

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Improved Charge-Trapping Characteristics of BaTiO3 by Zr Doping for Nonvolatile Memory Applications

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Scalability of Quasi-hysteretic FSM-based Digitally Controlled Single-inductor Dual-string Buck LED Driver To Multiple Strings

There has been growing interest in Single-Inductor Multiple-Output (SIMO) DC-DC converters due to its reduced cost and smaller form factor in comparison with using multiple single-output converters. An application for such a SIMO-based switching converter is to drive multiple LED strings in a multi-channel LED display. This paper proposes a quasi-hysteretic FSM-based digitally controlled Single-Inductor Dual-Output (SIDO) buck switching LED Driver operating in Discontinuous Conduction Mode (DCM) and extends it to drive multiple outputs. Based on the time-multiplexing control scheme in DCM, a theoretical upper limit of the total number of outputs in a SIMO buck switching LED driver for various backlight LED current values can be derived analytically. The advantages of the proposed SIMO LED driver include reducing the controller design complexity by eliminating loop compensation, driving more LED strings without limited by the maximum LED current rating, performing digital dimming with no additional switches required, and optimization of local bus voltage to compensate for variability of LED forward voltage (VF) in each individual LED string with smaller power loss. Loosely-binned LEDs with larger VF variation can therefore be used for reduced LED costs.postprin

Adaptive High-Bandwidth Digitally Controlled Buck Converter with Improved Line and Load Transient Response

Digitally controlled switching converter suffers from bandwidth limitation because of the additional phase delay in the digital feedback control loop. In order to overcome the bandwidth limitation without using a high sampling rate, this paper presents an adaptive third-order digital controller for regulating a voltage-mode buck converter with a modest 2x oversampling ratio. The phase lag due to the ADC conversion time delay is virtually compensated by providing an early estimation of the error voltage for the next sampling time instant, enabling a higher unity-gain bandwidth without compromising stability. An additional pair of low-frequency pole and zero in the third-order controller increases the low-frequency gain, resulting in faster settling time and smaller output voltage deviation during line transient. Both simulation and experimental results demonstrate that the proposed adaptive third-order controller reduces the settling time by 50% in response to a 1 V line transient and 30% in response to a 600 mA load transient, compared to the baseline static second-order controller. The fastest settling time is measured to be around 11.70 s, surpassing the transient performance of conventional digital controllers and approaching that of the state-of-the-art analog-based controllers.postprin

Nitrided La 2O 3 as charge-trapping layer for nonvolatile memory applications

Charge-trapping characteristics of La 2O 3 with and without nitrogen incorporation were investigated based on Al/Al 2O 3/La 2O 3/SiO 2Si (MONOS) capacitors. The physical properties of the high-k films were analyzed by X-ray diffraction and X-ray photoelectron spectroscopy. Compared with the MONOS capacitor with La 2O 3 as charge-trapping layer, the one with nitrided La 2O 3 showed a larger memory window (4.9 V at ±10-V sweeping voltage), higher program speed (4.9 V at 1-ms +14 V), and smaller charge loss (27% after 10 years), due to the nitrided La 2O 3 film exhibiting less crystallized structure and high trap density induced by nitrogen incorporation, and suppressed leakage by nitrogen passivation. © 2012 IEEE.published_or_final_versio

LaTiON/LaON as band-engineered charge-trapping layer for nonvolatile memory applications

Charge-trapping characteristics of stacked LaTiON/LaON film were investigated based on Al/Al 2O 3/LaTiON-LaON/SiO 2/Si (band-engineered MONOS) capacitors. The physical properties of the high-k films were analyzed by X-ray diffraction, transmission electron microscopy and X-ray photoelectron spectroscopy. The band profile of this band-engineered MONOS device was characterized by investigating the current-conduction mechanism. By adopting stacked LaTiON/LaON film instead of LaON film as charge-trapping layer, improved electrical properties can be achieved in terms of larger memory window (5.4 V at ±10-V sweeping voltage), higher program speed with lower operating gate voltage (2.1 V at 100-μs +6 V), and smaller charge loss rate at 125 °C, mainly due to the variable tunneling path of charge carriers under program/erase and retention modes (realized by the band-engineered charge-trapping layer), high trap density of LaTiON, and large barrier height at LaTiON/SiO 2 (2.3 eV). © 2012 The Author(s).published_or_final_versionSpringer Open Choice, 28 May 201

Spreading-resistance temperature sensor on silicon-on-insulator

A spreading-resistance temperature (SRT) sensor is fabricated on silicon-on-insulator (SOI) substrate and achieves promising characteristics as compared with similar SRT sensor on bulk silicon wafer. Moreover, experimental results show that the maximum operating temperature of thin-film (1.2 μm) SOI SRT sensor can reach 450 °C, much higher than 350 °C of thick-film (10 μm) SOI SRT sensor under the same current level. With complete oxide isolation, this sensor structure can be potentially used in low-power integrated sensors operating at temperatures as high as 450 °C.published_or_final_versio

Nb-doped Gd2O3 as charge-trapping layer for nonvolatile memory applications

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Latch-up characteristics of a trench-gate conductivity modulated power transistor

Conference Theme: Asia-Pacific Microelectronics 2000In this paper, a new conductivity modulated power transistor, called the Lateral Trench-Gate Bipolar Transistor (LTGBT), is presented. The current at which the latch-up occurs in the structure is estimated in comparison with that of the LIGBT. The latch-up current density for the LTGBT exhibits more than 7.7 times improvement over the LIGBT. The dependence of the latch-up current density on the design of the n+ and p+ cathode regions of the structure is also examined. The maximum controllable latch-up current density is found to increase with decreasing the space between the trench gate and the p+ cathode.published_or_final_versio

Nb-Doped La2O3 as Charge-Trapping Layer for Nonvolatile Memory Applications

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